{"id":"CVE-2025-63384","details":"A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.","modified":"2026-04-10T05:34:53.066963Z","published":"2025-11-10T20:15:49.013Z","references":[{"type":"PACKAGE","url":"https://github.com/chipsalliance/rocket-chip.git"},{"type":"EVIDENCE","url":"https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET"}],"affected":[{"ranges":[{"type":"GIT","repo":"https://github.com/chipsalliance/rocket-chip","events":[{"introduced":"0"},{"last_affected":"44b0b8249279d25bd75ea693b725d9ff1b96e2ab"}],"database_specific":{"versions":[{"introduced":"0"},{"last_affected":"1.6"}]}}],"versions":["v1.6"],"database_specific":{"source":"https://storage.googleapis.com/cve-osv-conversion/osv-output/CVE-2025-63384.json"}}],"schema_version":"1.7.5","severity":[{"type":"CVSS_V3","score":"CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N"}]}