{"id":"CVE-2023-34326","details":"The caching invalidation guidelines from the AMD-Vi specification (48882—Rev\n3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction\n(see stale DMA mappings) if some fields of the DTE are updated but the IOMMU\nTLB is not flushed.\n\nSuch stale DMA mappings can point to memory ranges not owned by the guest, thus\nallowing access to unindented memory regions.\n","modified":"2026-04-10T04:58:29.118546Z","published":"2024-01-05T17:15:08Z","related":["SUSE-SU-2023:4054-1","SUSE-SU-2023:4055-1","SUSE-SU-2023:4174-1","SUSE-SU-2023:4183-1","SUSE-SU-2023:4184-1","SUSE-SU-2023:4185-1","SUSE-SU-2023:4475-1","SUSE-SU-2023:4476-1","openSUSE-SU-2024:13442-1"],"references":[{"type":"ADVISORY","url":"https://xenbits.xenproject.org/xsa/advisory-442.html"}],"schema_version":"1.7.5","severity":[{"type":"CVSS_V3","score":"CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H"}]}